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industrial current/voltage output driver with programmable ranges AD5748 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features current output ranges: 4 ma to 21 ma, 0 ma to 21 ma 0.15% fsr total unadjusted error (tue) 5 ppm/c fsr typical output drift voltage output ranges: 0 v to 5 v, 0 v to 10.5 v, 10.5 v 0.05% fsr total unadjusted error (tue) 3 ppm/c fsr output drift flexible serial digital interface on-chip output fault detection pec error checking asynchronous clear function flexible power-up condition to 0 v or tristate power supply range av dd : +12 v ( 10%) to +24 v ( 10%) av ss : ?12 v ( 10%) to ?24 v ( 10%) output loop compliance to av dd ? 2.75 v temperature range: ?40c to +105c 32-lead, 5 mm 5 mm lfcsp package applications process control actuator control plcs general description the AD5748 is a single-channel, low cost, precision, voltage/ current output driver with hardware or software programmable output ranges. the software ranges are configured via an spi-/ microwire?-compatible serial interface. the AD5748 targets applications in plc and industrial process control. the analog input to the AD5748 is provided from a low voltage, single-supply, digital-to-analog converter (dac) and is internally conditioned to provide the desired output current/voltage range. the analog input range is 0 v to 4.096 v. the output current range is programmable across two current ranges: 4 ma to 21 ma and 0 ma to 21 ma. voltage output is provided from a separate pin that can be configured to provide 0 v to 5 v, 0 v to 10.5 v, or 10.5 v output range. analog outputs are short-circuit and open-circuit protected and can drive capacitive loads of 2 f and inductive loads of 0.1 h. the device is specified to operate with a power supply range from 12 v to 24 v. output loop compliance is 0 v to av dd ? 2.75 v. the flexible serial interface is spi- and microwire-compatible and can be operated in 3-wire mode to minimize the digital isolation required in isolated applications. the interface also features an optional pec error checking feature using crc-8 error checking, useful in indust rial environments where data communication corruption can occur. the device also includes a powe r-on-reset function, ensuring that the device powers up in a known state (0 v or tristate), and a asynchronous clear pin that sets the outputs to zero scale/midscale voltage output or the low end of the selected current range. an hw select pin is used to configure the part for hardware or software mode on power-up. note that the plots in the typical performance characteristics section of this data sheet contain information on the standard ranges, as released in the ad5750 / ad5750-1 data sheet. although the overranges have been tested, new plots were not generated and substitution data was used for plotting purposes. table 1. related device part number description ad5422 single-channel, 16-bit, serial input current source and voltage output dac
AD5748 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 functional block diagram .............................................................. 3 specifications ..................................................................................... 4 timing characteristics ................................................................ 7 absolute maximum ratings ............................................................ 9 esd caution .................................................................................. 9 pin configuration and function descriptions ........................... 10 typical performance characteristics ........................................... 12 voltage output ............................................................................ 12 current output ........................................................................... 16 terminology .................................................................................... 21 theory of operation ...................................................................... 22 software mode ............................................................................ 22 current output architecture .................................................... 24 driving inductive loads ............................................................ 24 power-on state of the AD5748 ................................................ 24 default registers at power-on ................................................. 25 reset function ............................................................................ 25 outen ........................................................................................ 25 software control ........................................................................ 25 hardware control ...................................................................... 27 transfer function ....................................................................... 27 detailed description of features .................................................. 28 output fault alertsoftware mode ....................................... 28 output fault alerthardware mode ..................................... 28 voltage output short-circuit protection ................................ 28 asynchronous clear (clear) ................................................. 28 current setting resistor ............................................................ 29 packet error checking ............................................................... 29 applications information .............................................................. 30 transient voltage protection .................................................... 30 thermal considerations ............................................................ 30 layout guidelines....................................................................... 30 galvanically isolated interface ................................................. 31 microprocessor interfacing ....................................................... 31 outline dimensions ....................................................................... 32 ordering guide .......................................................................... 32 revision history 3/10revision 0: initial version
AD5748 rev. 0 | page 3 of 32 functional block diagram clear vsense+ vout vsense? rext1 iout dvcc gnd a vdd gnd comp1 comp2 ad2/ r1 * ad1/ r2 * ad0/ r3 * avss clrsel hw select vin vref sclk/ outen * sdin/ r0 * sync/ rset * sdo/ vfault * input shift register and control logic status register vout range scaling iout range scaling vout short fault power- on reset fault/ temp * nc/ ifault * overtemp vout short fault iout open fault pec error reset avdd r2 r set r3 rext2 iout open fault AD5748 * denotes shared pin. software mode denoted by regular text, hardware mode denoted by italic text. for example, for fault/ temp pin, in software mode, this pin takes on fault function. in hardware mode, this pin takes on temp function. 08922-001 figure 1.
AD5748 rev. 0 | page 4 of 32 specifications av dd /av ss = 12 v ( 10%) to 24 v ( 10%), dvcc = 2.7 v to 5.5 v, gnd = 0 v. iout: r load = 300 . all specifications t min to t max , unless otherwise noted. table 2. parameter 1 min typ max unit test conditions/comments input voltage range output unloaded v in 0 to 4.096 v input leakage current ?1 +1 a reference input reference input voltage 4.096 v external reference needs to be exactly as stated; otherwise, accuracy errors show up as error in output input leakage current ?1 +1 a voltage output, v out output voltage ranges 0 5 v 0 10.5 v avdd must have minimum 1.3 v headroom ?10.5 +10.5 v avdd/avss must have minimum 1.3 v headroom accuracy total unadjusted error (tue) 2 ?0.3 +0.3 % fsr ?0.1 0.05 +0.1 % fsr t a = 25c relative accuracy (inl) ?0 .02 0.005 +0.02 % fsr bipolar zero error (offset at midscale) ?10 +10 mv 10.5 v range ?8 0.5 +8 mv t a = 25c, 10.5 v range bipolar zero error tc 3 1.5 ppm fsr/c 10.5 v range zero-scale error ?10 +10 mv 10.5 v range ?8 0.5 +8 mv t a = 25c, 10.5 v range zero-scale error tc 3 1 ppm fsr/c 10.5 v range zero-scale/offset error ?5 +5 mv 0 v to 10.5 v range ?4 0.5 +4 mv t a = 25c, 0 v to 10.5 v range ?3 +3 mv 0 v to 5 v range ?2.2 0.3 +2.2 mv t a = 25c, 0 v to 5 v range offset error tc 3 2 ppm fsr/c gain error ?0.05 +0.05 % fsr all ranges ?0.04 0.015 +0.04 % fsr t a = 25c gain error tc 3 0.5 ppm fsr/c full-scale error ?0.05 +0.05 % fsr all ranges ?0.04 0.015 +0.04 % fsr t a = 25c full-scale error tc 3 1.5 ppm fsr/c voltage output characteristics 3 headroom 1.3 v output unloaded short-circuit current 15 ma load 1 k capacitive load stability t a = 25c r load = 1 nf r load = 2 k 1 nf r load = 2 f external compensation capacitor required; see the driving inductive loads section dc output impedance 0.12 0 v to 5 v range, ? to ? step 7 s specified with 2 k || 220 pf, 0.05% 0 v to 5 v range, 40 mv input step 4.5 s specified with 2 k || 220 pf, 0.05% slew rate 2 v/s specified with 2 k || 220 pf output noise 2.5 v rms 0.1 hz to 10 hz bandwidth 45.5 v rms 100 khz bandwidth
AD5748 rev. 0 | page 5 of 32 parameter 1 min typ max unit test conditions/comments output noise spectral density 165 nv/ hz measured at 10 khz; specified with 2 k || 220 pf ac psrr ?65 db 200 mv, 50 hz/60 hz sine wave superimposed on power supply voltage dc psrr 10 v/v outputs unloaded current output, i out output current ranges 0 21 ma 4 21 ma accuracy, internal r set 4 total unadjusted error (tue) 2 ?0.5 +0.5 % fsr ?0.3 0.15 +0.3 % fsr t a = 25c relative accuracy (inl) ?0.02 0.01 +0.0 2 % fsr 4 ma to 21 ma, 0 ma to 21 ma offset error ?16 +16 a 4 ma to 21 ma, 0 ma to 21 ma ?10 +5 +10 a t a = 25c offset error tc 3 3 ppm fsr/c 4 ma to 21 ma, 0 ma to 21 ma gain error ?0.2 +0.2 % fsr 4 ma to 21 ma, 0 ma to 21 ma ?0.03 0.006 +0.03 % fsr t a = 25c gain tc 3 8 ppm fsr/c 4 ma to 21 ma, 0 ma to 21 ma full-scale error ?0.2 +0.2 % fsr 4 ma to 21 ma, 0 ma to 21 ma ?0.125 0.02 +0.125 % fsr t a = 25c full-scale tc 3 4 ppm fsr/c 4 ma to 21 ma, 0 ma to 21 ma accuracy, external r set 4 total unadjusted error (tue) 2 ?0.3 +0.3 % fsr ?0.1 0.02 +0.1 % fsr t a = 25c relative accuracy (inl) ?0.0 2 0.01 +0.02 % fsr 4 ma to 21 ma, 0 ma to 21 ma offset error ?14 +14 a 4 ma to 21 ma, 0 ma to 21 ma ?11 +5 +11 a t a = 25c offset error tc 3 2 ppm fsr/c 4 ma to 21 ma, 0 ma to 21 ma gain error ?0.08 +0.08 % fsr 4 ma to 21 ma, 0 ma to 21 ma ?0.07 0.02 +0.07 % fsr t a = 25c gain tc 1 ppm fsr/c 4 ma to 21 ma, 0 ma to 21 ma full-scale error ?0.1 +0.1 % fsr 4 ma to 21 ma, 0 ma to 21 ma ?0.07 0.02 +0.07 % fsr t a = 25c full-scale tc 3 2 ppm fsr/c 4 ma to 21 ma, 0 ma to 21 ma current output characteristics 3 current loop compliance voltage 0 av dd ? 2.75 v resistive load see comments chosen so that compliance is not exceeded inductive load see comments needs appropriate capacitor at higher inductance values; see the driving inductive loads section settling time 4 ma to 21 ma, full-scale step 8.5 s 250 load 120 a step, 4 ma to 21 ma range 1.2 ? s 250 load dc psrr 1 a/v output impedance 130 m digital input jedec compliant input high voltage, v ih 2 v input low voltage, v il 0.8 v input current ?1 +1 a per pin pin capacitance 5 pf per pin digital outputs 3 fault, ifault, temp, vfault output low voltage, v ol 0.4 v 10 k pull-up resistor to dvcc output low voltage, v ol 0.6 v at 2.5 ma output high voltage, v oh 3.6 v 10 k pull-up resistor to dvcc
AD5748 rev. 0 | page 6 of 32 parameter 1 min typ max unit test conditions/comments sdo output low voltage, v ol 0.5 0.5 v sinking 200 a output high voltage, v oh dvcc ? 0.5 dvcc ? 0.5 v sourcing 200 a high impedance output capacitance 3 pf high impedance leakage current ?1 +1 a power requirements positive analog supply, av dd 12 24 v 10% negative analog supply, av ss ?12 ?24 v 10% digital power supply, dv cc input voltage 2.7 5.5 v ai dd 4.4 5.2 ma output unloaded, output disabled, r3, r2, r1, r0 = 0, 1, 0, 1 5.2 6.2 ma current output enabled 5.2 6.2 ma voltage output enabled ai ss 2.0 2.5 ma output unloaded, output disabled, r3, r2, r1, r0 = 0, 1, 0, 1 2.5 3 ma current output enabled 2.5 3 ma voltage output enabled di cc 0.3 1 ma v ih = dvcc, v il = gnd power dissipation 108 mw av dd /av ss = 24 v, outputs unloaded 1 temperature range: ?40c to +105c; typical at +25c. 2 specification includes gain and offset errors over temper ature, and drift after 1000 hours, t a = 125c. 3 guaranteed by characterization, but not production tested. 4 see the current setting resistor section.
AD5748 rev. 0 | page 7 of 32 timing characteristics av dd /av ss = 12 v ( 10%) to 24 v ( 10%), dvcc = 2.7 v to 5.5 v, gnd = 0 v. vout: r load = 2 k, c l = 200 pf, iout: r load = 300 . all specifications t min to t max , unless otherwise noted. table 3. parameter 1 , 2 limit at t min , t max unit description t 1 20 ns min sclk cycle time t 2 8 ns min sclk high time t 3 8 ns min sclk low time t 4 5 ns min sync falling edge to sclk falling edge setup time t 5 10 ns min 16 th sclk falling edge to sync rising edge (on 24 th sclk falling edge if using pec) t 6 5 ns min minimum sync high time (write mode) t 7 5 ns min data setup time t 8 5 ns min data hold time t 9 , t 10 1.5 s max clear pulse low/high activation time t 11 5 ns min minimum sync high time (read mode) t 12 40 ns max sclk rising edge to sdo valid (sdo c l = 15 pf) t 13 10 ns min reset pulse low time 1 guaranteed by characterization, but not production tested. 2 all input signals are specified with t r = t f = 5 ns (10% to 90% of dv cc ) and timed from a voltage level of 1.2 v.
AD5748 rev. 0 | page 8 of 32 timing diagrams d15 12 16 d0 t 1 t 2 t 5 t 8 t 7 t 3 sclk sync sdin clea r vout t 10 t 9 t 13 reset t 4 t 6 08922-002 figure 2. write mode timing diagram sclk sdin sdo sync a2 a1 a0 r = 1 0 x x x x x x x x x x x x x x x x r3 r2 r1 r0 clrsel outen rset pec error over temp iout fault vout fault 12 16 t 11 t 12 0 8922-003 figure 3. readback mode timing diagram
AD5748 rev. 0 | page 9 of 32 absolute maximum ratings t a = 25c unless otherwise noted. transient currents of up to 100 ma do not cause scr latch-up. table 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter rating avdd to gnd ?0.3 v to +30 v avss to gnd +0.3 v to ?28 v avdd to avss ?0.3 v to +58 v dvcc to gnd ?0.3 v to +7 v vsense+ to gnd avss to avdd vsense? to gnd 5.0 v digital inputs to gnd ?0.3 v to dv cc + 0.3 v or 7 v (whichever is less) digital outputs to gnd ?0.3 v to dv cc + 0.3 v or 7 v (whichever is less) vref to gnd ?0.3 v to +7 v vin to gnd ?0.3 v to +7 v vout, iout to gnd avss to avdd operating temperature range, ?40c to +105c industrial storage temperature range ?65c to +150c junction temperature (t j max) 125c 32-lead lfcsp package ja thermal impedance 28c/w lead temperature jedec industry standard soldering j-std-020 esd (human body model) 3 kv esd caution
AD5748 rev. 0 | page 10 of 32 pin configuration and fu nction descriptions pin 1 indicator top view (not to scale) AD5748 1 sdo/vfault 2 clrsel 3 clear 4 dvcc 5 gnd 6 sync/rset 7 s clk/outen 8 sdin/r0 24 vsense+ 23 vout 22 vsense? 21 avss 20 comp1 19 comp2 18 iout 17 avdd 9 ad2/r1 10 ad1/r2 11 ad0/r3 12 rext2 13 r ext1 14 vref 15 vin 16 gnd 32 nc/i fault 31 fault/te mp 30 r eset 29 hw select 28 nc 27 n c 26 nc 25 nc notes 1. nc = no connect. 2 . the exposed paddle is tied to avss. 08922-00 4 figure 4. pin configuration table 4. pin function descriptions pin no. nemonic description 1 sdo/vfault serial data output (sdo). in software mode, this pin is used to cloc k data from the input shift register in readback mode. data is clocked out on the rising edge of sclk and is valid on the falling edge of sclk. this pin is a cmos output. short-circuit fault alert (vfault). in hardware mode, th is pin acts as a short-circuit fault alert pin and is asserted low when a short-circuit error is detected. this pin is an open-drain output and must be connected to a pull-up resistor. 2 clrsel in hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. in software mode, this pin is implemented as a logic or with the internal clrsel bit. 3 clear active high input. asserting this pin sets the output current/voltage to zero -scale code or midscale code of the range selected (user-selectable). clear is a logic or with the internal clear bit. in software mode, during power-up, the clear pin le vel determines the power-on condition of the voltage channel, which can be active 0 v or tristate. see the asynchronous clear (clear) section for more details. 4 dvcc digital power supply. 5 gnd ground connection. 6 sync /rset positive edge-sensitive latch ( sync ). in software mode, a rising edge parallel loads the input shift register data into the AD5748, also updating the output. resistor select (rset). in hardware mode, this pin chooses whether the internal or the external current sense resistor is used. if rset = 0, the external sense resistor is chosen. if rset = 1, the internal sense resistor is chosen. 7 sclk/outen serial clock input (sclk). in software mode, data is cloc ked into the input shift register on the falling edge of sclk. this pin operates at clock speeds of up to 50 mhz. output enable (outen). in hardware mode , this pin acts as an output enable pin. 8 sdin/r0 serial data input (sdin). in software mode , data must be valid on the falling edge of sclk. range decode bit (r0). in hardware mode, this pin, in conjunction with r1, r2, and r3, selects the output current/voltage range setting on the part. 9 ad2/r1 device addressing bit (ad2). in software mode, this pin, in conjunction with ad1 and ad0, allows up to eight devices to be addressed on one bus. range decode bit (r1). in hardware mode, this pin, in conjunction with r0, r2, and r3, selects the output current/voltage range setting on the part. 10 ad1/r2 device addressing bit (ad1). in software mode, this pin, in conjunction with ad2 and ad0 allows up to eight devices to be addressed on one bus. range decode bit (r2). in hardware mode, this pin, in conjunction with r0, r1, and r3, selects the output current/voltage range setting on the part.
AD5748 rev. 0 | page 11 of 32 pin no. mnemonic description 11 ad0/r3 device addressing bit (ad0). in software mode, this pin, in conjunction with ad1 and ad2, allows up to eight devices to be addressed on one bus. range decode bit (r3). in hardware mode, this pin, in conjunction with, r0, r1, and r2, selects the output current/voltage range setting on the part. 12, 13 rext2, rext1 a 15 k external current setting resistor can be conne cted between the rext1 and rext2 pins to improve the iout temperature drift performance. 14 vref buffered reference input. 15 vin buffered analog input (0 v to 4.096 v). 16 gnd ground connection. 17 avdd positive analog supply pin. 18 iout current output pin. 19, 20 comp2, comp1 optional compensation capacitor connections for the voltage output buffer. these are used to drive higher capacitive loads on the output. these pins also reduce overshoot on the output. care should be taken when choosing the value of the capacitor connected between the comp1 and comp2 pins because it has a direct influence on the settling t ime of the output. see the driving large capacitive loads section for further details. 21 avss negative analog supply pin. 22 vsense? sense connection for the negative voltage output load connection. this pin must stay within 3.0 v of ground for correct operation. 23 vout buffered analog output voltage. 24 vsense+ sense connection for the positive voltage output load connection. 25, 26, 27, 28 nc no connect. can be tied to gnd. 29 hw select this pin is used to configure the part to hardware or software mode. hw select = 0 selects software control. hw select = 1 selects hardware control. 30 reset resets the part to its power-on state. 31 fault/temp fault alert (fault). in software mode, this pin acts as a general fault alert pin. it is asserted low when an open circuit, short circuit, overtemperature error, or pec inte rface error is detected. this pin is an open-drain output and must be connected to a pull-up resistor. overtemperature fault (temp). in hardware mode, this pin acts as an overtemperature fault pin. it is asserted low when an overtemperature error is detected. this pi n is an open-drain output and must be connected to a pull-up resistor. 32 nc/ifault no connect (nc). in software mode, this pin is a no connect. instead, tie this pin to gnd. open-circuit fault alert (ifault). in hardware mode, this pin acts as an open-circuit faul t alert pin. it is asserted low when an open-circuit error is detected. this pin is an open-drain output and must be connected to a pull- up resistor. 33 (epad) exposed paddle the exposed paddle is tied to avss.
AD5748 rev. 0 | page 12 of 32 typical performance characteristics voltage output 0.0020 ?0.0030 ?0.0025 ?0.0020 ?0.0015 ?0.0010 ?0.0005 0 0.0005 0.0010 0.0015 04 . 0 9 6 3.511 2.926 2.341 1.755 1.170 0.585 inl (%fsr) v in (v) +5v +10v 10v av dd = +24v av ss = ?24v 08922-005 figure 5. integral nonlinearity error vs. v in 0.005 ?0.005 ?0.004 ?0.003 ?0.002 ?0.001 0 0.001 0.002 0.003 0.004 105 25 ?40 inl (%fsr) temperature (c) av dd = +24v av ss = ?24v +5v linearity, no load +10v linearity, no load 10v linearity, no load 08922-006 figure 6. integral nonlinearity error vs. temperature 0.006 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0.004 0.002 0 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 tue (%fsr) v in (v) +5v +10v 10v av dd = +24v av ss = ?24v 0 8922-007 figure 7. total unadjusted error vs. v in 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 105 25 ?40 tue (%fsr) temperature (c) +5v positive tue, no load +10v positive tue, no load 10v positive tue, no load +5v negative tue, no load +10v negative tue, no load 10v negative tue, no load 08922-008 figure 8. total unadjusted error vs. temperature 0.03 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 105 25 ?40 full-scale error (%fsr) temperature (c) +5v range, full-scale error +10v range, full-scale error 10v range, full-scale error 08922-009 figure 9. full-scale error vs. temperature 2.5 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 105 25 ?40 bipolar zero error (mv) temperature (c) 10v zero error av dd = +24v av ss = ?24v 08922-010 figure 10. bipolar zero error vs. temperature
AD5748 rev. 0 | page 13 of 32 0.020 ?0.025 ?0.020 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0.015 105 25 ?40 gain error (%fsr) temperature (c) av dd = +24v av ss = ?24v +5v gain, no load +10v gain, no load 10v gain, no load 08922-011 figure 11. gain error vs. temperature 2.5 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.5 2.0 1.0 105 25 ?40 zero-scale error (mv) temperature (c) av dd = +24v av ss = ?24v output unloaded +5v range +10v range 10v range 08922-012 figure 12. zero-scale error (offset error) vs. temperature 0.003 ?0.003 ?0.002 ?0.001 0 0.001 0.002 inl (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +5v linearity, no load +10v linearity, no load 10v linearity, no load 08922-013 figure 13. integral nonlinearity error vs. supply voltage 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +5v positive tue, no load +10v positive tue, no load 10v positive tue, no load +5v negative tue, no load +10v negative tue, no load 10v negative tue, no load 08922-014 figure 14. total unadjusted error vs. supply voltages 1.2 1.0 0.8 0.6 0.4 0.2 0 105 25 ?40 headroom (v) temperature (c) 10v av dd headroom, load off 08922-015 figure 15. av dd headroom, 10 v range, output set to 10 v, load off 0.05 ?0.05 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 0.04 15 ?15?13?11?9?7?5?3?1 1 3 5 7 9 1113 output voltage delta (v) source/sink current (ma) +5v range 10v range 08922-016 figure 16. source and sink capability of output amplifier
AD5748 rev. 0 | page 14 of 32 12 10 8 6 4 2 0 27221712 72 ?3?8 voltage (v) time (s) 08922-017 figure 17. full-scale positive step 12 10 8 6 4 2 0 27221712 72 ?3?8 voltage (v) time (s) 08922-018 figure 18. full-scale negative step 40 35 30 25 20 15 10 5 0 ?5 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 v out (mv) time (ms) 08922-019 figure 19. v out vs. time on power-up, load = 2 k || 200 pf ch1 5.00v ch2 20.0mv b w m1.0s a ch1 3.00v 1 2 0 8922-020 figure 20. v out enable glitch, load = 2 k || 1 nf 5v/div 1s/div 08922-021 figure 21. peak-to-peak noise (0.1 hz to 10 hz bandwidth) 100v/div 1s/div 08922-022 figure 22. peak-to-peak noise (100 khz bandwidth)
AD5748 rev. 0 | page 15 of 32 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 1.0 0.8 0.6 0.4 0.2 0 ?0.2 2.0 1.5 av dd v out 1.0 0.5 0 ?0.5 ?1.0 ?1.5 av dd (v) v out (v) time (ms) 08922-023 figure 23. av dd and v out vs. time on power-up
AD5748 rev. 0 | page 16 of 32 current output 0.004 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0.002 0 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 inl (%fsr) v in (v) av dd = +24v av ss = ?24v +4ma to +20ma 0ma to +20ma 0 8922-024 figure 24. integral nonlinearity error vs. v in , external r set resistor 0.004 ?0.012 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0.002 0 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 inl (%fsr) v in (v) av dd = +24v av ss = ?24v +4ma to +20ma 0ma to +20ma 0 8922-025 figure 25. integral nonlinearity error vs. v in , internal r set resistor 0.010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 inl (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +4ma to +20ma external r set linearity 0ma to +20ma external r set linearity 08922-026 figure 26. integral nonlinearity error, current mode, external r set sense resistor 0.010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 inl (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +4ma to +20ma internal r set linearity 0ma to +20ma internal r set linearity 08922-027 figure 27. integral nonlinearity error current mode, internal r set sense resistor 0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 tue (%fsr) v in (v) av dd = +24v av ss = ?24v +4ma to +20ma 0ma to +20ma 0 8922-028 figure 28. total unadjusted error vs. v in , external r set resistor 0.015 ?0.015 ?0.010 ?0.005 0 0.005 0.010 0 4.096 3.511 2.926 2.341 1.755 1.170 0.585 tue (%fsr) v in (v) av dd = +24v av ss = ?24v +4ma to +20ma 0ma to +20ma 0 8922-029 figure 29. total unadjusted error vs. v in , internal r set resistor
AD5748 rev. 0 | page 17 of 32 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +4ma to +20ma external r set positive tue 0ma to +20ma external r set positive tue +4ma to +20ma external r set negative tue 0ma to +20ma external r set negative tue 08922-030 figure 30. total unadjusted error current mode, external r set sense resistor 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) supply voltages (av dd /av ss ) +11.2/?10.8 15.0 24.0 26.4 +4ma to +20ma internal r set positive tue 0ma to +20ma internal r set positive tue +4ma to +20ma internal r set negative tue 0ma to +20ma internal r set negative tue 08922-031 figure 31. total unadjusted error current mode, internal r set sense resistor 105 25 ?40 temperature (c) 0.010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 inl (%fsr) +4ma to +20ma internal r set linearity 0ma to +20ma internal r set linearity av dd = +24v av ss = ?24v 08922-032 figure 32. inl vs. temperature, internal r set sense resistor 105 25 ?40 temperature (c) 0.010 ?0.010 ?0.008 ?0.006 ?0.004 ?0.002 0 0.002 0.004 0.006 0.008 inl (%fsr) +4ma to +20ma external r set linearity 0ma to +20ma external r set linearity av dd = +24v av ss = ?24v 08922-033 figure 33. inl vs. temperature, external r set sense resistor 105 25 ?40 temperature (c) 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) +4ma to +20ma internal r set positive tue 0ma to +20ma internal r set positive tue +4ma to +20ma internal r set negative tue 0ma to +20ma internal r set negative tue 08922-034 figure 34. total unadjusted error vs. temperature, internal r set sense resistor 0.10 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.02 0.04 0.06 0.08 tue (%fsr) +4ma to +20ma external r set positive tue 0ma to +20ma external r set positive tue +4ma to +20ma external r set negative tue 0ma to +20ma external r set negative tue 105 25 ?40 temperature (c) 08922-035 figure 35. total unadjusted erro r vs. temperature, external r set sense resistor
AD5748 rev. 0 | page 18 of 32 6 ?6 ?4 ?2 0 2 4 zero-scale error (a) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma external r set 0ma to +20ma external r set 08922-036 figure 36. zero-scale error vs. temperature, external r set sense resistor 25 ?20 ?15 ?10 ?5 0 5 10 15 20 zero-scale error (a) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma internal r set 0ma to +20ma internal r set 20ma internal r set 24ma internal r set 08922-037 figure 37. zero-scale error vs. temperature, internal r set sense resistor 0.04 ?0.04 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 full-scale error (%fsr) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma external r set 0ma to +20ma external r set 08922-040 figure 38. full-scale error vs. temperature, external r set sense resistor 0.04 ?0.06 ?0.04 ?0.05 ?0.03 ?0.02 ?0.01 0 0.01 0.02 0.03 full-scale error (%fsr) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma internal r set 0ma to +20ma internal r set 08922-041 figure 39. full-scale error vs. temperature, internal r set sense resistor 0.020 0.015 ?0.015 ?0.010 ?0.005 0 0.005 0.010 gain error (%fsr) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma external r set 0ma to +20ma external r set 08922-042 figure 40. gain error vs. temperature, external r set sense resistor 0.08 ?0.10 ?0.08 ?0.06 ?0.04 ?0.02 0 0.04 0.02 0.06 gain error (%fsr) 105 25 ?40 temperature (c) av dd = +24v av ss = ?24v +4ma to +20ma internal r set 0ma to +20ma internal r set 08922-043 figure 41. gain error vs. temperature, internal r set sense resistor
AD5748 rev. 0 | page 19 of 32 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 compliance (v) 105 25 ?40 temperature (c) av dd compliance 08922-044 figure 42. output comp liance vs. temperature tested when i out = 10.8 ma 12 10 8 6 4 2 0 ?2 0.000010 ?0.000010 ?0.000008 ?0.000006 ?0.000004 ?0.000002 0 0.000002 0.000004 0.000006 0.000008 10 v dd i out ?10?8?6?4?202468 v dd (v) i out (a) time (ms) 08922-045 figure 43. output current vs. time on power-up 0 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 8 ?2?101234567 i out (v) time (s) 08922-046 figure 44. output current vs . time on output enable 0.025 0.020 0.015 0.010 0.005 0 686154 484134 282114 81 ?12 ?6 current (a) time (s) 08922-047 figure 45. 4 ma to 20 ma output current step 3000 2500 2000 1500 1000 500 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 di cc (a) logic level (v) dv cc = 5v dv cc = 3v 08922-048 figure 46. di cc vs. logic input voltage
AD5748 rev. 0 | page 20 of 32 6 5 4 3 2 1 0 ?1 ?2 ?3 ai dd /ai ss (ma) av dd /av ss (v) 10.8 15.0 24.0 26.4 ai dd ai ss 08922-049 figure 47. ai dd /ai ss vs. av dd /av ss , v out = 0 v 6 5 4 3 2 1 0 ?1 ?2 ?3 ai dd /ai ss (ma) av dd /av ss (v) 10.8 15.0 24.0 26.4 ai dd ai ss 08922-050 figure 48. ai dd /ai ss vs. av dd /av ss , i out = 0 ma
AD5748 rev. 0 | page 21 of 32 terminology tot a l un a dju s te d e r ror ( t u e ) tue is a measure of the output error taking all the various errors into account: inl error, offset error, gain error, and output drift over supplies, temperature, and time. tue is expressed as a percentage of full-scale range (% fsr). relative accuracy or integral nonlinearity (inl) inl is a measure of the maximum deviation, in % fsr, from a straight line passing through the endpoints of the output driver transfer function. a typical inl vs. input voltage plot can be seen in figure 5 . bipolar zero error bipolar zero error is the deviation of the actual vs. ideal half- scale output of 0 v/0 ma with a bipolar range selected. a plot of bipolar zero error vs. temperature can be seen in figure 10 . bipolar zero tc bipolar zero tc is a measure of the change in the bipolar zero error with a change in temperature. it is expressed in ppm fsr/c. full-scale error full-scale error is the deviation of the actual full-scale analog output from the ideal full-scale output. full-scale error is expressed as a percentage of full-scale range (% fsr). full-scale tc full-scale tc is a measure of the change in the full-scale error with a change in temperature. it is expressed in ppm fsr/c. gain error gain error is a measure of the span error of the output. it is the deviation in slope of the output transfer characteristic from the ideal expressed in % fsr. a plot of gain error vs. temperature can be seen in figure 11 . gain error tc gain error tc is a measure of the change in gain error with changes in temperature. gain error tc is expressed in ppm fsr/c. zero-scale error zero-scale error is the deviation of the actual zero-scale analog output from the ideal zero-scale output. zero-scale error is expressed in millivolts (mv). zero-scale tc zero-scale tc is a measure of the change in zero-scale error with a change in temperature. zero-scale error tc is expressed in ppm fsr/c. offset error offset error is a measurement of the difference between vout (actual) and vout (ideal) expres sed in millivolts (mv) in the linear region of the transfer function. it can be negative or positive. output voltage settling time output voltage settling time is the amount of time it takes for the output to settle to a specified level for a half-scale input change. slew rate the slew rate of a device is a limitation in the rate of change of the output voltage. the output slewing speed is usually limited by the slew rate of the amplifier used at its output. slew rate is measured from 10% to 90% of the output signal and is expressed in v/s. current loop voltage compliance current loop voltage compliance is the maximum voltage at the iout pin for which the output current is equal to the programmed value. power-on glitch energy power-on glitch energy is the impulse injected into the analog output when the AD5748 is powered on. it is specified as the area of the glitch in nv-sec. power supply rejection ratio (psrr) psrr indicates how the output is affected by changes in the power supply voltage.
AD5748 rev. 0 | page 22 of 32 theory of operation the AD5748 is a single-channel, precision, voltage/current output driver with hardware or software programmable output ranges. the software ranges are configured via an spi-/ microwire-compatible serial interface. the analog input to the AD5748 is provided from a low voltage, single-supply, digital-to-analog converter and is internally conditioned to provide the desired output current/voltage range. the analog input range is 0 v to 4.096 v. the output current range is programmable across two current ranges: 4 ma to 21 ma and 0 ma to 21 ma. the voltage output is provided from a separate pin that can be configured to provide 0 v to 5 v, 0 v to 10.5 v, or 10.5 v output ranges. the current and voltage outputs are available on separate pins. only one output can be enabled at one time. the output range is selected by programming the r3 to r0 bits in the control register (see table 6 and table 7 ). figure 49 and figure 50 show a typical configuration of the AD5748 in software mode and in hardware mode, respectively, in an output module system. the hw select pin selects whether the part is configured in software or hardware mode. the analog input to the AD5748 is provided from a low voltage, single-supply, digital-to-analog converter (dac) such as the ad506x or ad566x, which provides an output range of 0 v to 4.096 v. the supply and reference for the dac, as well as the reference for the AD5748, can be supplied from a reference such as the adr392 . the AD5748 can operate from supplies up to 26.4 v. software mode in current mode, software-selectable output ranges include 0 ma to 21 ma, and 4 ma to 21 ma. in voltage mode, software-selectable output ranges include 0 v to 5 v, 0 v to 10.5 v, and 10.5 v. vsense+ vsense? vin sclk vdd refin sdi/din sdo sync1 sync sdo sdin sclk ad506x ad566x mcu vout 0v to +5v, 0v to +10.5v, 10.5v iout 4ma to 21ma, 0ma to 21ma vout range scale iout range scale vout short fault iout open fault overtemp fault pec error status register serial interface vref hw select fault adp1720 adr392 v dd a gnd v ss avdd gnd avss AD5748 08922-051 figure 49. typical system configuration in software mode (pull-up resistors not shown for open-drain outputs)
AD5748 rev. 0 | page 23 of 32 vsense+ vsense? r3 r2 r1 r0 output range select pins vin sclk vdd refin sdi/din sdo sync1 ad506x ad566x mcu vout 0v to +5v, 0v to +10.5v, 10.5v iout 4ma to +21ma, 0ma to +21ma vout range scale iout range scale vref temp vfault ifault adp1720 adr3192 v dd a gnd v ss AD5748 outen hw select dvcc avdd gnd avss 08922-052 figure 50. typical system configuration in hardware mode using internal dac reference (pull-up resistors not shown for open-dra in outputs) table 5. suggested parts for use with AD5748 dac reference power accuracy description ad5660 internal adp1720 1 12-bit inl mid end system, single channel, internal reference ad5664r internal n/a n/a mid end system, quad channel, internal reference ad5668 internal n/a n/a mid end system, octal channel, internal reference ad5060 adr434 adp1720 16-bit inl high end system, single channel, external reference ad5064 adr434 n/a n/a high end system, quad channel, external reference ad5662 adr392 2 adr392 2 12-bit inl mid end system, single channel, external reference ad5664 adr392 2 n/a n/a mid end system, quad channel, external reference 1 adp1720 input range up to 28 v. 2 adr392 input range up to 15 v.
AD5748 rev. 0 | page 24 of 32 current output architecture the voltage input from the analog input vin pin (0 v to 4.096 v) is either converted to a current (see figure 51 ), which is then mirrored to the supply rail so that the application simply sees a current source output with respect to an internal reference voltage, or buffered and scaled to output a software-selectable unipolar or bipolar voltage range (see figure 52 ). the reference is used to provide internal offsets for range and gain scaling. the selectable output range is programmable through the digital interface. rset r2 r3 iout avdd t1 iout range scaling rangedecode from interface vin t2 vref a2 a1 0 8922-059 figure 51. current output configuration vout range scaling vsense+ vout vsense? vout short fault range decode from interface vin (0v to 4.096v) vref 08922-054 figure 52. voltage output driving inductive loads when driving inductive or poorly defined loads, connect a 0.01 f capacitor between iout and gnd. this ensures stability with loads beyond 50 mh. there is no maximum capacitance limit. the capacitive component of the load may cause slower settling. voltage output amplifier the voltage output amplifier is capable of generating both unipolar and bipolar output voltages. it is capable of driving a load of 1 k in parallel with 1.2 f (with an external compensa- tion capacitor on the comp1 and comp2 pins). the source and sink capabilities of the output amplifier can be seen in figure 16 . the slew rate is 2 v/s. internal to the device, there is a 2.5 m resistor connected between the vout and vsense+ pins and similarly between the vsense? pin and the internal device ground. should a fault condition occur, these resistors act to protect the AD5748 by ensuring that the amplifier loop is closed so that the part does not enter into an open-loop condition. the vsense? pin can work in a common-mode range of 3 v with respect to the remote load ground point. the current and voltage are output on separate pins and cannot be output simultaneously. this allows the user to tie both the current and voltage output pins together and configure the end system as a single-channel output. driving large capacitive loads the voltage output amplifier is capable of driving capacitive loads of up to 1 f with the addition of a nonpolarized compensation capacitor between the comp1 and comp2 pins. without the compensation capacitor, up to 20 nf capacitive loads can be driven. care should be taken to choose an appropriate value for the c comp capacitor. this capacitor, while allowing the AD5748 to drive higher capacitive loads and reduce overshoot, increases the settling time of the part and, therefore, affects the bandwidth of the system. considered values of this capacitor should be in the range 100 pf to 4 nf depending on the trade- off required between settling time, overshoot, and bandwidth. power-on state of the AD5748 on power-up, the AD5748 sens es whether hardware or software mode is loaded and sets the power-up conditions accordingly. in software spi mode, the power-up state of the output is depen- dent on the state of the clear pin. if the clear pin is pulled high, then the part powers up, driving an active 0 v on the output. if the clear pin is pulled low, then the part powers up with the voltage output channel in tristate mode. in both cases, the current output channel powers up in a tristate condition (0 ma). this allows the voltage and current outputs to be connected together if desired. to put the part into normal operation, the user must set the outen bit in the control register to enable the output and, in the same write, set the output range configuration using the r3 to r0 range bits. if the clear pin is still high (active) during this write, the part automatically clears to its normal clear state as defined by the programmed range and by the clrsel pin or clrsel bit (see the asynchronous clear (clear) section for more details). the clear pin must be taken low to operate the part in normal mode. the clear pin is typically driven directly from a microcontroller. in cases where the power supply for the AD5748 supply may be independent of the microcontroller power supply, the user can connect a weak pull-up resistor to dvcc or a pull-down resistor to ground to ensure that the correct power-up condition is achieved independent of the microcontroller. a 10 k pull- up/pull-down resistor on the clear pin should be sufficient for most applications. if hardware mode is selected, the part powers up to the condi- tions defined by the r3 to r0 range bits and the status of the outen or clear pin. it is recommended to keep the output disabled when powering up the part in hardware mode.
AD5748 rev. 0 | page 25 of 32 default registers at power-on the AD5748 power-on reset circuit ensures that all registers are loaded with zero code. in software spi mode, the part powers up with all outputs dis- abled (outen bit = 0). the user must set the outen bit in the control register to enable the output and, in the same write, set the output range configuration using the r3 to r0 bits. if hardware mode is selected, the part powers up to the conditions defined by the r3 to r0 bits and the status of the outen pin. it is recommended to keep the output disabled when powering up the part in hardware mode. reset function in software mode, the part can be reset using the reset pin (active low) or the reset bit (reset = 1). a reset disables both the current and voltage outputs to their power-on condition. the user must write to the outen bit to enable the output and, in the same write, set the output range configuration. the reset pin is a level-sensitive input; the part stays in reset mode as long as the reset pin is low. the reset bit clears to 0 following a reset command to the control register. in hardware mode, there is no reset. if using the part in hardware mode, the reset pin should be tied high. outen in software mode, the output can be enabled or disabled using the outen bit in the control register. when the output is disabled, both the current and voltage channels go into tristate. the user must set the outen bit to enable the output and simultaneously set the output range configuration. in hardware mode, the output can be enabled or disabled using the outen pin. when the output is disabled, both the current and voltage channels both go into tristate. the user must write to the outen pin to enable the output. it is recommended that the output be disabled when changing the ranges. software control software control is enabled by connecting the hw select pin to ground. in software mode, the AD5748 is controlled over a versatile 3-wire serial interface that operates at clock rates of up to 50 mhz. it is compatible with spi, qspi?, microwire, and dsp standards. input shift register the input shift register is 16 bits wide. data is loaded into the device msb first as a 16-bit word under the control of a serial clock input, sclk. data is clocked in on the falling edge of sclk. the input shift register consists of 16 control bits, as shown in table 6 . the timing diagram for this write operation is shown in figure 2 . the first three bits of the input shift register are used to set the hardware address of the AD5748 device on the printed circuit board (pcb). up to eight devices can be addressed per board. bit d11, bit d1, and bit d0 must always be set to 0 during any write sequence. table 6. input shift register contents for a write operationcontrol register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a2 a1 a0 r/ w 0 r3 r2 r1 r0 clrsel outen clear rset reset 0 0 table 7. input shift register descriptions bit description a2, a1, a0 used in association with the ad2, ad1, and ad0 external pins to determine which part is being addressed by the system controller a2 a1 a0 function 0 0 0 addresses part with pin ad2 = 0, pin ad1 = 0, pin ad0 = 0 0 0 1 addresses part with pin ad2 = 0, pin ad1 = 0, pin ad0 = 1 0 1 0 addresses part with pin ad2 = 0, pin ad1 = 1, pin ad0 = 0 0 1 1 addresses part with pin ad2 = 0, pin ad1 = 1, pin ad0 = 1 1 0 0 addresses part with pin ad2 = 1, pin ad1 = 0, pin ad0 = 0 1 0 1 addresses part with pin ad2 = 1, pin ad1 = 0, pin ad0 = 1 1 1 0 addresses part with pin ad2 = 1, pin ad1 = 1, pin ad0 = 0 1 1 1 addresses part with pin ad2 = 1, pin ad1 = 1, pin ad0 = 1 r/ w indicates a read from or a write to the addressed register
AD5748 rev. 0 | page 26 of 32 bit description r3, r2, r1, r0 selects output configuration in conjunction with rset rset r3 r2 r1 r0 output configuration 0 0 0 0 0 4 ma to 21 ma (external 15 k current sense resistor) 0 0 0 0 1 0 ma to 21 ma (external 15 k current sense resistor) 0 0 0 1 0 n/a 0 0 0 1 1 n/a 0 0 1 0 0 n/a 0 0 1 0 1 0 v to 5 v 0 0 1 1 0 n/a 0 0 1 1 1 n/a 0 1 0 0 0 n/a 0 1 0 0 1 n/a 0 1 0 1 0 0 v to 10.5 v 0 1 0 1 1 n/a 0 1 1 0 0 10.5 v 0 1 1 0 1 n/a 0 1 1 1 0 n/a 0 1 1 1 1 n/a 1 0 0 0 0 4 ma to 21 ma (internal current sense resistor) 1 0 0 0 1 0 ma to 21 ma (internal current sense resistor) 1 0 0 1 0 n/a 1 0 0 1 1 n/a 1 0 1 0 0 n/a 1 0 1 0 1 0 v to 5 v 1 0 1 1 0 n/a 1 0 1 1 1 n/a 1 1 0 0 0 n/a 1 1 0 0 1 n/a 1 1 0 1 0 0 v to 10.5 v 1 1 0 1 1 n/a 1 1 1 0 0 10.5 v 1 1 1 0 1 n/a 1 1 1 1 0 n/a 1 1 1 1 1 n/a clrsel sets clear mode to zero scale or midscale. see the asynchronous clear (clear) section clrsel function 0 clear to 0 v 1 clear to midscale in unipolar mode; clear to zero scale in bipolar mode outen output enable bit. this bit must be set to 1 to enable the outputs clear software clear bit, active high rset select internal/external current sense resistor rset function 1 select internal current sense resistor; used with the r3 to r0 bits to select range 0 select external current sense resistor; used with the r3 to r0 bits to select range reset resets the part to its power-on state
AD5748 rev. 0 | page 27 of 32 readback operation readback mode is activated by selecting the correct device address (a2, a1, a0) and then setting the r/ w bit to 1. by default, the sdo pin is disabled. after having addressed the AD5748 for a read operation, setting r/ w to 1 enables the sdo pin and sdo data is clocked out on the 5 th rising edge of sclk. after the data has been clocked out on sdo, a rising edge on sync disables (tristate) the sdo pin again. status register data (see ) and control register data are both available during the same read cycle. table 8 the status bits comprise four read-only bits. they are used to notify the user of specific fault conditions that occur, such as an open circuit or short circuit on the output, overtemperature error, or an interface error. if any of these fault conditions occurs, a hardware fault is also asserted low, which can be used as a hardware interrupt to the controller. see the detailed description of features section for a full explanation of fault conditions. hardware control hardware control is enabled by connecting the hw select pin to dvcc. in this mode, the r3, r2, r1, and r0 pins in conjunction with the rset pin are used to configure the output range, as per table 7 . in hardware mode, there is no status register. the fault condi- tions (open circuit, short circuit, and overtemperature) are available on pin ifault, pin vfault, and pin temp. if any one of these fault conditions is set, then a low is asserted on the specific fault pin. ifault, vfault, and temp are open-drain outputs and, therefore, can be connected together to allow the user to generate one interrupt to the system controller to commu- nicate a fault. if hardwired in this way, it is not possible to isolate which fault occurred in the system. transfer function the AD5748 consists of an internal signal conditioning block that maps the analog input voltage to a programmed output range. the available analog input range is 0 v to 4.096 v. for all ranges, both current and voltage, the AD5748 imple- ments a straight linear mapping function. 0 v maps to the lower end of the selected range; 4.096 v maps to the upper end of the selected range. table 8. input shift register contents for a read operationstatus register msb lsb d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a2 a1 a0 1 0 r3 r2 r1 r0 clrsel outen rset pec error over temp iout fault vout fault table 9. status bit options bit description pec error this bit is set if there is an interface error detected by crc-8 error checking. see the detailed description of features section. vout fault this bit is set if there is a short circuit on the vout pin. iout fault this bit is set is there is an open circuit on the iout pin. over temp this bit is set if the AD5748 co re temperature exceeds approximately 150c.
AD5748 rev. 0 | page 28 of 32 detailed description of features o utput fault alertsoftware mode i n software mode, the AD5748 is equipped with one fault pin; this is an open-drain output allowing several AD5748 devices to be connected together to one pull-up resistor for global fault detection. in software mode, the fault pin is forced active low by any one of the following fault scenarios: ? the voltage at iout attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. the internal circuitry that develops the fault output avoids using a comparator with window limits because this requires an actual output error before the fault output becomes active. instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 v of remaining drive capability. thus, the fault output activates slightly before the compliance limit is reached. because the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and an output error does not occur before the fault output becomes active. ? a short is detected on the voltage output pin (vout). the short-circuit current is limited to 15 ma. ? an interface error is detected due to a packet error checking (pec) failure. see the packet error checking section. ? if the core temperature of the AD5748 exceeds approximately 150c. o utput fault alerthardware mode i n hardware mode, the AD5748 is equipped with three fault pins: vfault, ifault, and temp. these are open-drain outputs allowing several AD5748 devices to be connected together to one pull-up resistor for global fault detection. in hardware control mode, these fault pins are forced active by any one of the following fault scenarios: ? open-circuit detect. the voltage at iout attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. the internal circuitry that develops the fault output avoids using a comparator with window limits because this requires an actual output error before the fault output becomes active. instead, the signal is generated when the internal amplifier in the output stage has less than approximately 1 v of remaining drive capability. thus, the fault output activates slightly before the compliance limit is reached. because the compari- son is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and an output error does not occur before the fault output becomes active. if this fault is detected, the ifault pin is forced low. ? a short is detected on the voltage output pin (vout). the short-circuit current is limited to 15 ma. if this fault is detected, the vfault pin is forced low. ? if the core temperature of the AD5748 exceeds approx- imately 150c. if this fault is detected, the temp pin is forced low. voltage output short-circuit protection under normal operation, the voltage output sinks and sources up to 12 ma and maintains the specified operation. the maxi- mum current that the voltage output delivers is 15 ma; this is the short-circuit current. asynchronous clear (clear) clear is an active high clear that allows the voltage output to be cleared to either zero-scale code or midscale code and is user-selectable via the clrsel pin or the clrsel bit of the input shift register, as described in table 7 . (the clear select feature is a logical or function of the clrsel pin and the clrsel bit.) the current loop output clears to the bottom of its programmed range. when the clear signal is returned low, the output returns to its programmed value or a new value if programmed. a clear operation can also be performed via the clear command in the control register. table 10. clrsel options clrsel output clear value unipolar output voltage range unipolar current output range 0 0 v zero scale; for example: 4 ma on the 4 ma to 21 ma range 0 ma on the 0 ma to 21 ma range 1 midscale midscale; for example: 12.5 ma on the 4 ma to 21 ma range 10.5 ma on the 0 ma to 21 ma range
AD5748 rev. 0 | page 29 of 32 current setting resistor referring to figure 1 , r set is an internal sense resistor as part of the voltage-to-current conversion circuitry. the nominal value of the internal current sense resistor is 15 k. to allow for over- range capability in current mode, the user can also select the internal current sense resistor to be 14.7 k, giving a nominal 2% overrange capability. this feature is available in the 0 ma to 21 ma and 4 ma to 21 ma current ranges. the stability of the output current value over temperature is dependent on the stability of the value of r set . as a method of improving the stability of the output current over temperature, an external low drift resistor can be connected to the rext1 and rext2 pins of the AD5748, which can be used instead of the internal resistor. the external resistor is selected via the input shift register. if the external resistor option is not used, the rext1 and rext2 pins should be left floating. packet error checking to verify that data has been received correctly in noisy environ- ments, the AD5748 offers the option of error checking based on an 8-bit (crc-8) cyclic redundancy check. the device controlling the AD5748 should generate an 8-bit frame check sequence using the following polynomial: c ( x ) = x 8 + x 2 + x 1 + 1 this is added to the end of the data-word, and 24 data bits are sent to the AD5748 before taking sync high. if the AD5748 receives a 24-bit data frame, it performs the error check when sync goes high. if the check is valid, then the data is written to the selected register. if the error check fails, the fault pin goes low and bit d3 of the status register is set. after reading this register, this error flag is cleared automatically and the fault pin goes high again. sclk sdin sync update on sync high d15 (msb) d0 (lsb) 16-bit data 16-bit data transer?no error checking sclk sdin sync fault update after sync high only if error check passed fault goes low if error check fails d23 (msb) d8 (lsb) d7 d0 16-bit data 8-bit fcs 16-bit data transer with error checking 08922-055 figure 53. pec error checking timing
AD5748 rev. 0 | page 30 of 32 applications information transient voltage protection the AD5748 contains esd protection diodes that prevent damage from normal handling. the industrial control environment can, however, subject i/o circuits to much higher transients. to protect the AD5748 from excessively high voltage transients, external power diodes and a surge current limiting resistor may be required, as shown in figure 54 . the constraint on the resistor value is that, during normal operation, the output level at iout must remain within its voltage compliance limit of av dd ? 2.75 v, and the two protection diodes and resistor must have appropri- ate power ratings. further protection can be added with transient voltage suppressors if needed. iout avdd avdd avss AD5748 r p r load 0 8922-056 figure 54. output transient voltage protection thermal considerations it is important to understand the effects of power dissipation on the package and on junction temperature. the internal junction temperature should not exceed 125c. the AD5748 is packaged in a 32-lead lfcsp 5, 5 mm 5 mm package. the thermal impedance, ja , is 28c/w. it is important that the devices are not operated under conditions that cause the junction tempera- ture to exceed its junction temperature. worst-case conditions occur when the AD5748 is operated from the maximum av dd (26.4 v) while driving the maximum current (24 ma) directly to ground. the quiescent current of the AD5748 should also be taken into account, nominally ~4 ma. the following calculations estimate maximum power dissipation under these worst-case conditions, and determine maximum ambient temperature based on the power dissipation: power dissipation = 26.4 v 28 ma = 0.7392 w temp increase = 28c 0.7392 w = 20.7c maximum ambient temp = 125c ? 20.7c = 104.3c these figures assume that proper layout and grounding techniques are followed to minimize power dissipation, as outlined in the layout guidelines section. layout guidelines in any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. the pcb on which the AD5748 is mounted should be designed so that the AD5748 lies on the analog plane. the AD5748 should have ample supply bypassing of 10 f in parallel with 0.1 f on each supply located as close to the package as possible, ideally right up against the device. the 10 f capacitors are the tantalum bead type. the 0.1 f capaci- tor should have low effective series resistance (esr) and low effective series inductance (esi) such as the common ceramic types, which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. in systems where there are many devices on one board, it is often useful to provide some heat sinking capability to allow the power to dissipate easily. a d5748 avss plane board 08922-057 figure 55. paddle connection to board the AD5748 has an exposed paddle beneath the device. this paddle is connected to the avss supply for the part. for opti- mum performance, special considerations should be used to design the motherboard and to mount the package. for enhanced thermal, electrical, and board level performance, the exposed paddle on the bottom of the package is soldered to the correspond- ing thermal land paddle on the pcb. thermal vias are designed into the pcb land paddle area to further improve heat dissipation. the avss plane on the device can be increased (as shown in figure 55 ) to provide a natural heat sinking effect.
AD5748 rev. 0 | page 31 of 32 galvanically isolated interface in many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled to protect and isolate the controlling circuitry from any hazardous common-mode voltages that may occur. the i coupler? family of products from analog devices, inc., provides voltage isolation in excess of 5.0 kv. the serial loading structure of the AD5748 makes it ideal for isolated interfaces because the number of interface lines is kept to a minimum. figure 56 shows a 4-channel isolated interface using an adum1400 . for further information, visit www.analog.com/icouplers . decode encode v ia v oa to sclk v ib v ob to sdin v ic v oc to sync v id v od to clear serial clock out serial data out sync out control out controller adum1400 1 1 additional pins omitted for clarity. decode encode decode encode decode encode 08922-058 figure 56. isolated interface microprocessor interfacing microprocessor interfacing to the AD5748 is via a serial bus that uses a protocol compatible with microcontrollers and dsp processors. the communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a sync signal. the AD5748 requires a 16-bit data-word with data valid on the falling edge of sclk.
AD5748 rev. 0 | page 32 of 32 compliant to jedec standards mo-220-vhhd-2 011708-a 0.23 0.18 outline dimensions 0.30 0.20 ref 0.80 max 0.65 typ 0.05 max 0.02 nom 12 max 1.00 0.85 0.80 seating plane 0.08 coplanarity 1 32 8 9 25 24 16 17 0.50 0.40 0.30 3.50 ref 0.50 bsc pin 1 indi c ator top view 5.00 bsc sq 4.75 bsc sq 3.25 3.10 sq 2.95 pin 1 indicator 0.60 max 0.60 max 0.25 min exposed pad (bottom view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 57. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-2) dimensions shown in millimeters ordering guide model 1 tue accuracy analog input range external reference temperature range package description package option AD5748acpz 0.3% v out , 0.5% i out 0 v to 4.096 v 4.096 v ?40c to +105c 32-lead lfcsp_vq cp-32-2 AD5748acpz-rl7 0.3% v out , 0.5% i out 0 v to 4.096 v 4.096 v ?40c to +105c 32-lead lfcsp_vq cp-32-2 1 z = rohs compliant part. ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08922-0-3/10(0)

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